Exemplary embodiments of the present invention relate generally to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device including vertical channel layers and an operating method thereof.
Number of memory cells in a limited chip area can be increased by configuring a semiconductor memory device to include a three dimensional (3-D) structured memory array in which the memory cells are vertically stacked. In the 3-D structured memory array, channel layers of the memory cells are formed in a direction vertical to a semiconductor substrate, and word lines surrounding the vertical channel layers at specific intervals are formed in a cell region.
However, in a peripheral region, components of the semiconductor device, such as transistors, are formed to have a common 2-D structure. After the memory cells in the cell region are formed, the transistors in the peripheral region are formed.
Since the memory cells are vertically stacked in the cell region, a difference of thickness between the cell region and the peripheral region may increase, and forming the transistors in the peripheral region may become more complex.